OpenSBI "Domain0 Name: root": what a domain is

OpenSBI domains are the M-mode-level isolation primitive on RISC-V: the closest analogue to ARM's secure partitions. Each domain owns a subset of the SoC's HARTs (hardware threads) and a subset of the physical address space, and OpenSBI enforces PMP boundaries so one domain can't access another's memory.

On a StarFive VisionFive V2 the Boot HART report prints:

Domain0 Name              : root
Domain0 Boot HART         : 1
Domain0 HARTs             : 0*,1*,2*,3*,4*
Domain0 Region00          : 0x0000000002000000-0x000000000200ffff (I)
Domain0 Region01          : 0x0000000040000000-0x000000004007ffff ()
Domain0 Region02          : 0x0000000000000000-0xffffffffffffffff (R,W,X)
Domain0 Next Address      : 0x0000000040200000
Domain0 Next Mode         : S-mode

Decoded:

• Name: root: the default single-domain configuration. All HARTs, all memory, one namespace. Every OpenSBI build ships with a root domain; boards that don't configure custom domains just get this one.
• Boot HART: 1: HART ID 1 is selected as the S-mode entry point. On a 5-HART SoC (JH7110 = 4× U74 + 1× monitor S7), HART 0 is often the monitor and gets masked out of the Linux boot; U74 core 1 becomes the Linux boot HART.
• **HARTs: 0*,1*,2*,3*,4***: all five HARTs assigned to Domain0. The * suffix indicates the HART is enabled in this domain.
• Regions: the physical memory ranges the domain can access. Region 02 (0x0-0xffffffffffffffff (R,W,X)) is unrestricted access to the full 64-bit address space; the earlier regions carve out specific reservations (Region 00 at 0x2000000 is typically CLINT MMIO with I-flag = instruction-side).

When multi-domain matters: on a heterogeneous SoC (e.g. one where a real-time RISC-V core needs its own memory island isolated from the Linux HARTs), you'd configure two domains and let OpenSBI enforce PMP separation. On a single-purpose board like a VF2 running Linux across all HARTs, one root domain is expected.