Decode · RISC-V
DDR version dc2e84f0: the closed StarFive ddrinit blob
DDR version: dc2e84f0.The very first console line on a StarFive VisionFive V2 boot log is often just:
DDR version: dc2e84f0.This is the StarFive-signed DRAM-init blob for the JH7110 SoC: a small proprietary firmware that runs before U-Boot SPL, brings up the DDR controller and trains DRAM, and then hands control to U-Boot SPL loaded from SD card. The hex string dc2e84f0 is a build-identifier hash StarFive uses to version their blob.
Why this matters for the "RISC-V is fully open" story: OpenSBI itself is open source. So is U-Boot. So is the Linux kernel. But the pre-M-mode DRAM-init blob is not, and neither is the JH7110 boot ROM.
The blob is packaged as part of StarFive's U-Boot fork and is what makes it possible for the platform to actually reach DRAM at all: until DDR is initialized, U-Boot SPL has nowhere to load itself into. StarFive publishes updates to the blob periodically; each update ships with a different version hash.
Reverse engineering: community efforts have started on reversing the ddrinit blob to produce a fully-open alternative (analogous to what happened with the Raspberry Pi's start.elf on the VideoCore side). As of 2026 the work is incomplete: no drop-in open replacement exists yet.
Practical impact: if you're using a VF2 as an "everything auditable, nothing closed" reference board (a common RISC-V talking point), this line is where that story breaks down. The M-mode is open; the pre-M-mode isn't.
References
Full walkthrough: /blog/riscv-boot-lifecycle
Source log: /samples/bootintel-6.txt
Have a boot log with something you can't decode? Paste it into the free fingerprinter. It identifies bootloader / kernel / SoC / autoboot exposure client-side, nothing uploaded.