rv64imafdcbx: decoding the OpenSBI ISA string

The OpenSBI Boot HART report on a StarFive VisionFive V2 prints Boot HART Base ISA: rv64imafdcbx. Character-by-character decoding:

• rv64: 64-bit base integer ISA (RV64I is the baseline).
• i: the integer register extension (implicit in RV64I, printed again for compatibility).
• m: integer multiply / divide.
• a: atomic memory operations (LR/SC, AMO*).
• f: single-precision floating-point.
• d: double-precision floating-point.
• c: compressed 16-bit instructions (a large fraction of RV64 code is emitted as compressed for size).
• b: bit-manipulation extension (Zba/Zbb/Zbs/Zbc were ratified in 2021 as part of the "B" umbrella).
• x: vendor extensions bit. On the JH7110 U74 core this is set even though the specific vendor extension isn't enumerated.

The trailing b and x are the interesting parts. SiFive documents the U74 core in the JH7110 as RV64GC (equivalent to rv64imafdc). The extra b and x in the OpenSBI string are a display artifact: a slightly permissive base-ISA string emitter, not an assertion that the silicon implements those extensions. Confirming this: the same log a few lines later prints Boot HART ISA Extensions : none, meaning no beyond-baseline extensions are actually enumerated.

Practical consequence: later in the same boot log, U-Boot proper reports the CPU as rv64imacu: a narrower feature set. That's the ISA U-Boot itself was compiled against, and it's a better ground-truth for "what does the running software actually use" than the OpenSBI display string.

Debugging tip: if you're targeting a specific extension and want to know whether the hardware implements it, don't rely on the OpenSBI base-ISA string: check the ISA-extensions line beneath it, or grep the kernel dmesg for CPU features: on ARM-family terminology.