Decode · RISC-V

MEDELEG = 0xb109 on RISC-V: what the mask means

Boot HART MEDELEG         : 0x000000000000b109

MEDELEG is the RISC-V Machine Exception Delegation register: a bitmask specifying which synchronous exceptions get delegated from M-mode to S-mode (the kernel) instead of being handled by M-mode firmware (OpenSBI) itself.

The common value 0xb109 decodes bit-by-bit against the RISC-V Privileged Spec exception-code table:

  • Bit 0 (0x1): Instruction address misaligned
  • Bit 3 (0x8): Breakpoint
  • Bit 8 (0x100): Environment call from U-mode (user-ecall)
  • Bit 12 (0x1000): Instruction page fault
  • Bit 13 (0x2000): Load page fault
  • Bit 15 (0x8000): Store/AMO page fault

Adding those: 0x1 | 0x8 | 0x100 | 0x1000 | 0x2000 | 0x8000 = 0xb109.

This is the standard shape for a Linux-capable RISC-V board. Every synchronous exception the kernel normally handles is delegated. M-mode-only causes (M-mode ecall, illegal instructions in M-mode) stay with OpenSBI.

The paired MIDELEG register does the same for interrupts; see MIDELEG = 0x222 for its typical Linux value.

Debugging: if the kernel is failing to handle a specific exception (e.g. page faults getting eaten and never reaching the kernel handler), grep the OpenSBI Boot HART report for the MEDELEG value and confirm the corresponding bit is set.

References

Full walkthrough: /blog/riscv-boot-lifecycle

Source log: /samples/bootintel-6.txt

More decoders: /decode · /faq

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