MIDELEG = 0x222 on RISC-V: what the mask means

MIDELEG is the RISC-V Machine Interrupt Delegation register: a bitmask specifying which M-mode interrupts get delegated down to S-mode (the kernel) instead of being handled by M-mode firmware (OpenSBI) itself.

The common value 0x222 decodes bit-by-bit:

• Bit 1 (0x2): SSI, Supervisor Software Interrupt (IPIs between HARTs, delivered via ecall/SBI)
• Bit 5 (0x20): STI, Supervisor Timer Interrupt (the kernel scheduling timer)
• Bit 9 (0x200): SEI, Supervisor External Interrupt (device interrupts routed via PLIC)

Adding those: 0x2 | 0x20 | 0x200 = 0x222.

This is the standard shape for a Linux-capable RISC-V board. Every one of the three interrupts the kernel normally handles at S-mode is delegated. M-mode-only interrupts (MSI, MTI, MEI) stay with OpenSBI.

The paired MEDELEG register does the same for synchronous exceptions (page faults, ecalls, misaligned accesses). A common Linux-capable value is 0xb109; see MEDELEG = 0xb109.

Debugging: if you're chasing a mysterious OpenSBI hang on a RISC-V board, MIDELEG is one of the first things to check: a value with bits missing means S-mode isn't getting an interrupt it expects, and the kernel will stall waiting for it.